1. Field of the Invention
The present invention relates generally to a voltage divider. More particularly, the present invention relates to a voltage divider which is less susceptible to having the voltage divider output affected by alternate current paths provided by parasitic transistors and capacitors.
2. Description of the Background Art
Voltage dividers are widely used on most integrated circuits. Voltage dividers provide additional voltages needed in the operation of an integrated circuit, avoid the need for additional voltage supply pins on the integrated circuit packaging, and avoid the need to route additional voltage supply lines through out the integrated circuit. However, voltage dividers can fail to provide the anticipated voltages on integrated circuits because of parameter variations in the circuit devices and unintended parasitic structures that are an inevitable result of the integrated circuit fabrication process.
Referring now to FIG. 1, a circuit diagram of a prior art voltage divider is shown, implemented in a MOSFET technology. FIG. 1 illustrates a standard voltage divider circuit to produce an output voltage equal to one third of the input voltage. Transistor P1 has its source 100 connected to its substrate 101 and its gate 102 connected to its drain 103. Transistor P2 has its source 104 connected to its substrate 105 and its gate 106 connected to its drain 107. Transistor P3 has its source 108 connected to its substrate 109 and its gate 110 connected to its drain 111. Input voltage V1 is connected to the source terminal 100 and substrate bias 101 for P1, the source terminal 104 of P2 is connected to the drain terminal 103 of P1, the source terminal 108 of P3 is connected to the drain terminal 107 of P2, and V2 is the voltage divider output from the source terminal 108 for P3 whose drain terminal 111 is connected to ground.
Two fundamental assumptions used in the design of such voltage dividers are that the same amount of current is flowing through all the transistors in the voltage divider, and that the transistors each have the same threshold voltage and device transconductance (i.e., the same MOSFET channel width-to-length ratio). In this case, each transistor will have the same voltage drop between drain and source. If a transistor has a smaller device transconductance, it will have a larger voltage drop between drain and source than the other transistors. If a transistor has a larger device transconductance, it will have a smaller voltage drop between drain and source than the other transistors. But device transconductance varies according to the geometry of the transistor dimensions and can be controlled much more tightly than the threshold voltage.
The threshold voltage of each transistor depends on several factors, including the substrate bias of the transistor. If a set of MOS devices, having different biases on their sources, had their substrates connected to a power supply, then their threshold voltages would be different and the voltage divider's output (i.e. V2) would not be at its predicted value. To avoid this problem, the substrates 101, 105, and 109 are respectively connected to sources 100, 104, and 108. Under certain bias conditions, such as when V1 is less than an integer multiple of the thresholds of the MOS devices P1, P2 and P3, the current through the MOS devices decreases significantly. When this occurs, the substrate biases at nodes 104 and 108 become sensitive to currents in the parasitic devices inherent to the CMOS process. Thus, the currents in the parasitic devices have a significant effect on the currents in the MOS devices. In specific, lateral NPNs which have their collectors connected to the wells of the MOS transistors may conduct current to the point of keeping the voltage V2 less than an integer divider of the voltage at V1, regardless of what the V1 voltage might otherwise have been.
What is needed is a voltage divider circuit in which the output is less susceptible to parasitic effects that can change the desired output voltage.